If we now HALT the CPU, the internal clocks runs further, and so the WD-timers decrease until they reach 0x0000 (all timers are 16 Bit) and issue a warm-start reset. Same if we program the flash. The software loaded into the internal SRAM of the OMAP does not reset the WD timers, nor did they stop them, so a reset is issued. What is curious is, that on reading it does not seem to have this problem, but on writing... maybe different RAMcodes are used by Segger and one has a bug?
You may also read this doc from TI, where i get valuable information from: "OMAP5910/5912 Applications Processor Timers Reference Guide (SPRU891)".
Now, let me quote some interesting parts of this doc and add my comments
"The OMAP5912 has one MPU watchdog timer, one DSP watchdog timer, and one reserved 32-KHz watchdog timer. The watchdog timers reset or generate an interrupt to MPU or DSP when they reach timeout"
Timeout means, the counter value of the WD register reaches 0x0000
"They can be used to detect user programs stuck in an infinite loop, loss of program control, or a runaway condition"
e.g. if we Flash the unit
"The 32-KHz OS timer is able to generate periodical interrupts to the OS. This is used to keep track of the current time to control the operation of the device drivers, and also for OS scheduling purposes. If the OMAP chip is in deep sleep mode, it can also be used to wake up the system."
"Using the reserved 32-KHz watchdog timer is not supported. It needs to be disabled upon reset."
Now, what does that mean? Hope they will describe how to disabled those useless shit. If you read further the document, there is a GOTCHA:
"There are three watchdog timers inside the OMAP5912: one MPU watchdog timer, one DSP watchdog timer, and one reserved 32-KHz watchdog timer. Using the 32-KHz watchdog is not supported. Upon system reset, it needs to be disabled before it expires (in approximately 19s) via the following procedure:"
Hey, 19 seconds? This may be the thing we are looking after!! Let's see how they disable it:
Code: Select all
(*(volatile int*)0xFFFEB048) = 0xAAAA;
// wait until the write operation is completed
while ( ((*(volatile int *)0xFFFEB034) & 0x10) == 0x10 );
(*(volatile int*)0xFFFEB048) = 0x5555;
// wait until the write operation is completed
while ( ((*(volatile int *)0xFFFEB034) & 0x10) == 0x10 );
"The MPU watchdog timer also has the wakeup capability, as it resets both the MPU and DSP upon timeout. The DSP watchdog timer only resets the DSP when its counter expires."
Good to now...
"The features of the MPU/DSP private timers are as follows:
* 32-bit down count
* Interrupt to MPU/DSP when the timer expires
* Programmable timer period
* Auto-reload mode and one-shot mode
* On-the-fly read capability"
The MPU and DSP WDs are feed from the system-clock (CK_REF), which is produced from the external 12 MHz oscillator on the board:
The time a WD fires depends on this criterias:
1.) The frequency of the timer reference clock for the MPU/DSP private timer:
2.) The value of the prescaler bit field (PTV) in the MPU_/DSP_CNTL_TIMER register. The input reference clock to the timer is divided by 2(PTV+1). The PTV value is in the range from 0 to 7:
3.) The values of the load registers: MPU_LOAD_TIMER and DSP_LOAD_TIMER_HI/_LO.
Equation to determine the timer interrupt period for the MPU private timer: TMPU_Timeout = TMPU_ref_clk * (<MPU_LOAD_TIMER>+1) * 2(PTV+1)
For the DSP private timer: TDSP_Timeout = TDSP_ref_clk * (<DSP_LOAD_TIMER_HI, LO>+1) * 2(PTV+1)
Where TMPU_ref_clk and TDSP_ref_clk are the periods of the input reference clocks for the MPU and DSP private timers.
Interesting part:
"Before the MPU/DSP subsystem can enter any of the low power states, the MPU/DSP timer reference clock must be stopped in the following two ways:
1.) Set the EN_TIMCK bit in the MPU_/DSP_IDLECT2 register to 0 to force the clock to stop.
2.) Leave the EN_TIMCK bit in the MPU_/DSP_IDLECT2 register as 1, but stop all the MPU/DSP private timers by configuring the ST bit in the
MPU_/DSP_CNTL_TIMER register and set the IDLTIM_ARM/_DSP bit to 1. Setting the IDLTIM_ARM/_DSP bit to 1 causes the input reference clock to be stopped in conjunction with MPU/DSP clock when the idle mode is entered."
I wonder if we disable the clock source for the timers, if they would also halt the WD timers?
"Upon reset, the MPU/DSP timer module is in the following state:
1.) The input reference clock is from DPLL1 (ARM_CKCTL[ARM_TIMXO]/DSP_CKCTL[DSP_TIMXO] = 1).
2.) The input reference clock is stopped (EN_TIMCK bit is 0 in the ARM_/DSP_IDLECT2 register).
3.) The input clock is not enabled inside timer module (CLOCK_ENABLE bit is 0 in the MPU_/DSP_CNTL_TIMER register).
4.) The timer is in one-shot mode.
5.) The timer is stopped (ST bit is 0 in the MPU_/DSP_CNTL_TIMER register)."
Good to now.
... to be continued ...
