Anyway, to unsecure the device, the following steps are needed if the backdoor key (8 bytes long) are not known:
- Execute a mass erase command to the internal flash (program + data erased)
- execute a blank check on the flashes (only if this returns "all blank" the next steps are done)
- program the "Flash Security Word" (offset 0x0414) bits corresponding to the CFMSEC[SEC] field to "Flash memory not secured" (0b10)
- RESET the device into expanded mode (MODA=0, MODB=1) to execute boot code from external memory.
Currently, it have only a vague vision of how to do this. Beside the JTAG E-ICE there is also a Nexus 2 debug interface, but i guess i can do it by JTAG only. After i am able to connect to the chip i next try to issue the mass erase command. This command is from the CFM (Common-Flash-Module) commandset, described in chapter 15 of the reference manual.
The CFM get's it's commands through the "CFM Command Register (CFMCMD)", a 8-Bit register (only 7 Bits used) located at memory address 0xFC0F0024.
It knows these commands:
0x05 Blank Check
0x06 Page Erase Verify
0x20 Program Word/Half Word
0x40 Page Erase
0x41 Mass Erase
0x65 Data Signature
In order to generate a "mass ersase" we need to write "0x41" at 0xFC0F0024, right after reset into extended chip mode. Let's take a look into the docs:
"The mass erase operation will erase all Flash memory addresses using an embedded algorithm. All of the Flash (data and program) must be unsecured before this operation. After a mass erase, the Flash will be secured unless user writes to the security configuration word in Flash."
1. Write to any Flash memory address to start the command write sequence for the mass erase command. The specific address and data written during the mass erase command write sequence will be ignored.
2. Write the mass erase command, 0x41, to the CFMCMD register.
3. Write 0b1 to CBEIF to clear it, and to launch the mass erase command.
If any Flash logical sector is protected, the PVIOL flag in the CFMUSTAT register will set during the command write sequence and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the CFMUSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered.
So there must be some kind of "sequence" to launch CFM commands. Just writing to the register does not seem to be sufficient. Also, the execution depends on some other flags and they have a runtime (sure), which is reflected through readable flags. We need to "wait" for execution to be finished before issueing the next command. Here is what the docs say about the command sequence:
The Flash command controller is used to supervise the command write sequence to execute blank check, page erase verify, program, page erase, mass erase and data signature algorithms.
A specific sequence, consisting of three steps, must be strictly followed, with writes to the CFM not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows:
1. Write to one or more addresses in the Flash memory.
2. Write a valid command to the CFMCMD register.
3. Launch the command by writing a 0b1 to CFMUSTAT[CBEIF] (which clears the flag).
This is excatly what we seen above. One must write to an address (which is a 32bit write operation), which does not do anything without the now following write of the command to execute. But also this does not do anything unless the "GO" flag is raised in the last step, by writing a bit. After this we need to watch the bit until it is cleared (0) to show us, the command was executed.
But there are some stakes to climb first:
Prior to issuing any commands, it is necessary to write the CFMCLKD register to set the ratio between the IP bus clock frequency and fNVMOP such that fNVMOP is within the range of 150 KHz to 200 KHz. 
because after playing around a bit i powered the unit off and after turning it on it would not start any more. First, i thought i did something wrong in wiring or JTAG setup, because i could still read the Chip-ID and connect via JTAG but could not halt the CPU to access RAM or FLASH.
